1. Field of the Invention
The present invention relates to a semiconductor device, semiconductor package design, and components mounting therein, for reducing the noise occurring in the power feed line (wiring) of the semiconductor devices which handle high-speed signals for use in information-processing apparatus and the like.
2. Description of the Related Art
In the semiconductor devices that handle high-speed signals, the simultaneous switching output (SSO) noise generated by simultaneous switching of a large number of switching elements, each formed up of a CMOS and others, is becoming a problem. There are two types of SSO noise. One type is Off-Chip SSO noise due to the switching of the switching elements (such as the CMOS of an output butter) that are used to transmit off-chip signals between independent semiconductor elements. The other type is On-Chip SSO noise due to the switching of the switching elements (such as the CMOS's in the core circuit of a pre-buffer or control system) that are used to transmit on-chip signals.
Of the two types, On-Chip SSO noise, in particular, is the greater in time constant (i.e., the time required for the noise to attenuate is as long as on the order of nanoseconds). On-Chip SSO noise, therefore, poses a significant problem due to the fact that during the handling of high-speed signals exceeding a Giga-bit per second(Gbps) level, the noise generated by the next signal is superimposed on the noise generated by the previous signal. In a prior art, there has been a method in which an independent power supply line is provided in such a control circuit and an output buffer each in order that the noise generated by the control circuit does not become routed around and induced into the output buffer (refer to Japanese Patent Laid-Open No. Hei 5-29531).
As with a prior art, however, the method in which an independent power supply line is provided in the control circuit and the output buffer each, has involved the following problems:
(1) Increased number of power supply and grounding pins
(2) Increased inductance in power feed lines
Above item (1) means an increase in the number of semiconductor package and semiconductor device pins due to the provision of an independent power supply/grounding line in the control circuit and the output buffer each, and increases the dimensions and cost of the semiconductor device.
Above item (2) means that since two power feed lines are formed in a limited area, the resulting decrease in the width of the power feed line increases inductance, resulting in noise reduction being adversely affected.